IPC recently released an update to IPC-6012. Revision F covers qualification and performance specifications for rigid PCBs. Over the next few weeks, we’ll be discussing not only what the changes are, but how they can affect PCB design and manufacturing. Check back each week for additional insights into the new standard.
Section 3.3.1 Edge Plating New Paragraph Added to Edges
When printed board edge plating is specified, the following shall apply:
Plating separation from internal anchors (see IPC-2228) along the plated edge is not allowed. Edge wall pull-away from the dielectric shall be acceptable provided all the dimensional requirements are met. Plating voids shall not exceed 3 locations within the perimeter of the plated edge and not be greater than 1.27 mm [0.050in] in any length. Nodules on plated edges shall be acceptable as long as they are not loose and do not violate the overall printed board dimensions. Exposed bare copper is allowed on edges of breakaway (processing) tabs after final profile routing. Metallic burrs at breakaway (processing) tabs are acceptable as long as they are not loose and/or do not affect fit and function. Plated edge wrap onto the surface shall be within the dimensional limits of 3.5.1.
IPC-6012 revision F and IPC-2228, which was released in Oct 2022, are the first IPC documents that address design and performance requirements for edge plated printed boards. IPC-2228 is an excellent guideline for designing an edge plated PCB. See IPC-2228 Section 6.4.
Here are a few edge plated design considerations:
- Wrap the copper. Copper plating on the edge of the PCB has very low peel strength. The high outer layer copper peel strength in a typical PCB is accomplished by coatings on the copper foil that promote adhesion between prepreg and the copper foil. A plated edge of the PCB is milled/routed by a router bit which leaves a smooth almost polished surface. This smooth surface has electroless copper deposited and does not have any benefit of an adhesion promoter. Wrapping the copper onto the outer layer surface will take advantage of the copper foil adhesion promoters that anchor the top and bottom of the edge plating. Edge plating can easily peel off the edge if the design has no wrap plating. It is recommended to wrap the top and bottom surface by .63mm[0.025”]. While this value seems large keep in mind that the profile most PCBs is .254mm[0.010], and for the worst case scenario it is beneficial for adequate wrapping of the copper onto the outer layer copper.
- Extend copper to the edge of the PCB. Edge plating adhesion can be improved by extending copper beyond the edge of the PCB. The copper will be exposed by the milling/routing operation where edge plating is desired. The exposed copper will act as anchors for the edge plating which reduces “pull away.”
Here is an exaggerated example of edge plating pull away.
- Edge plating should only connect to the ground net. It is very important to pull back copper for all other layers where edge plating is desired.
- Pull back all copper on all layers for non-plated edges, include the allowed demarcation tolerance.
- Allow for generous demarcation tolerance between edge plated and non-plated edge of the PCB. The demarcation is created by a milling/ routing operation and as the spindle is rotating (at high speeds) the plunge of the bit is fairly clean but the pull out can pull the low peel strength edge plating. These pulls can range from target location to up to 0.020” additional pull and loss of edge plating of the side of the PCB. See example below.
- Understand the rules for edge plating in IPC-2228 (Released Oct 2022) section 6.4.
- Allow for generous dimensional tolerances for the demarcation of the transition from non-plated to plated edge. The demarcation/transition is not exact. Accuracy of demarcation of +/-0.025” would be beneficial.
- Only extend copper for ground layers pull back all other layers.
- For non-plated edges pull back copper on all layers.
- Document on your procurement documentation that copper to the edge of the PCB is by design.
- Edge plating should be used for ground shielding and not as a conductor. Position accuracy and length accuracy is not practical.
Table 1-2 Default Requirements
IPC-6012 default Table 1-2 is an often overlooked or unknown table that exists in all of the performance specifications IPC-6012, IPC-6013 and IPC-6018. These tables provide fabricator allowances to process and fabricate a PCB when the procurement documentation does not state the requirements for the following attributes.
New changes in table 1-2 are highlighted in YELLOW.
As a rule, IPC documents do not provide background as to why the changes are made or the cause and effects that the changes bring. Summit, with the help of this blog series, has been sharing the changes and the impact on the PCBs to help the industry to better understand the benefits of the newest revision and insight how and why these changes are needed.
Here is a short summary of the three changes and how and why they have come about.
Surface finish ENIG.
With the common usage of ENIG over Tin/Lead finishes, fabricators use less and less Tin/Lead finishes and it is not uncommon to find ENIG processing inhouse, with Tin/Lead processing subcontracted to an outside service. Additionally, running a Hot Air Solder Leveling HASL can incur over $25k per month in electrical power costs. ENIG surface finish also provides a uniform coplanar surface that is beneficial to assembling SMT components. The new change has a “cut in date”. All initial releases of a drawing will still follow the old rule of Tin/Lead only when a surface finish not specified. Starting with initial release dates on the drawing as of October 1, 2023 when a finish is not specified the fabricator may use ENIG, Tin/lead, or Pb-Free solder coating (another change to table 1-2). This will allow the fabricator to make the most cost effective, and efficient finish between the 3 finishes listed in Table 1-2.
The minimum dielectric has new lower default value of 65um [2,560u”]. This new change will allow fabricators to make dielectric thickness decisions for HDI/Laser drilled dielectrics without requesting thickness lower than the previous revisions minimum allowance of 90um[3,543u”]. Most microvia dielectrics use nominal thicknesses between 75um-100um[3,000u”-4,000u”]. This nominal range would either violate the old minimum or would always be on the edge of being noncompliant. This new change will prevent jobs being placed on hold in the Front End Engineering process, or deviation requests on finished product to allow for a lower minimum dielectric.
Solder Coated Pb-free
Fabricators will be able to use Pb-free solder coating if the surface finish is not specified. This will reduce the need to have HASL systems that run both Tin/Lead and PB-free systems in the same factory.
- The default surface finish will now have multiple options. If these options need to be controlled, it will be necessary to have the surface finish specified in the incoming procurement documentation.
- Dielectric minimums will be lower and withstanding voltages should be reviewed in high voltage designs.
- Allowance of Pb-free solder coating may introduce solder incompatibilities.
Section 188.8.131.52.1 Evidence of Etchback
Evidence of Etchback (When Specified) When only evidence of etchback (i.e. visual evidence of lateral removal of resin and/or glass fibers) is specified by procurement documentation, no more than two layers per hole shall show zero etchback. All other layers shall have etchback greater than zero.
This is a new section that has been added to section 184.108.40.206, and it is very important to understand and apply correctly.
When the procurement documentation allows for evidence of etchback there is an allowance for no evidence of etchback on no more than 2 layers. This new rule helps for high aspect ratio holes at greater than 10:1 and have small diameter drilled holes, typically .25mm [0.010”] or less. For these small diameter holes it is difficult to achieve evidence of etchback in the center of the hole and it does impact yields. The new rule allows for 2 layers in the middle of a plated hole to have no evidence of etchback. This change will be highly beneficial for improving fabrication yields.
Reflow and thermal shock testing of plated holes via IPC-TM-650 methods 2.6.27 and 220.127.116.11 with etchback, evidence of etchback, or no etchback have demonstrated the ability to pass reflow and thermal shocks. These results support this allowance in this revision of IPC-6012 rev F.
When applying the rule there must be some internal layers that show evidence, but in the event of stackups with more than 4 layers this rule is applied when evidence of etchback is specified.
Below is an example of a 12:1 aspect ratio with 1 layer with no evidence of etchback. Rejected in IPC-6012 rev E and now acceptable in IPC-6012 rev F. Please consider that source inspection training will be needed for correct evaluation of this section.
Section 18.104.22.168.1 Minimum Dielectric Spacing
If the minimum dielectric is unspecified, a new minimum dielectric spacing will go into effect for drawings with an initial release date after December 31, 2023. The new rule going into effect 1/1/2024 will have a minimum of 65um [0.00256”] when the minimum dielectric is not specified. For designs released before the cutoff date the old minimum dielectric rule will remain for those designs. The minimum dielectric before the cutoff date was 90um [0.003543”] and will remain so because of the cutoff date 12/31/2023.
So why the change? Microvias
Typical microvia stack ups will target a dielectric between 60um-100um [0.0025” to 0.004”] to manage the microvia aspect ratio. If a HDI design does not specify minimum dielectric for the expected range, it is easy for the finished PCB to measure below the previously allowed minimum thickness of 90um [0.003543”]. To prevent delays and rejecting parts that need a lower minimum, fabricators need to present a request for a new minimum allowed dielectric to ship finished product. New designs will no longer have this potential delay.
After 12/31/2023, new initial released HDI designs can be planned and released to manufacturing without requesting a new minimum dielectric. This new rule will reduce time consuming delays to request an AABUS (as agreed between user and supplier) for finished product or a new design that is the planning stage.
- This rule only applies if the initial release is after 12/31/2023.
- All designs with initial release before 1/1/2024 will follow the old rule.
- Both thickness and cut in dates are in IPC-6012 rev F section 22.214.171.124.1
- This does not apply to revision changes.
- Source inspection training will be needed for correct evaluation of this section.
IPC-6012 revision E section 126.96.36.199.3 – Dimples and Protrusions
Microvia dimples and protrusions are no longer AABUS. IPC-6012 revision E section 188.8.131.52.3 second paragraph started with “Requirements for protrusions (bumps) or depressions (dimples) in blind copper filled microvias shall be AABUS.
Revision F now has a new table 3-14 (3-14 is no longer the table for Internal Layer Foil Thickness after Processing) Table 3-14 is now titled “Depression and Protrusion in Copper Filled Microvias.”
|Designed Hole Diameter||greater than 0.15 mm [0.006 in]||less than or equal to 0.15 mm [0.006 in]|
|Filled Via Depression (Dimple) - Maximum||50 µm [1,969 µin]||25 µm [984 µin]|
|Filled Via Protrusion (Bump) - Maximum||25 µm [984 µin]||25 µm [984 µin]|
Note 1: Applies to microvias in lands intended to be soldered at assembly.
What is interesting with this addition is that the table does not use classes but is broken down by laser via diameters. Depression/dimple allowance is 25µm/0.000984” for a microvia that is less than or equal to 0.15mm/0.006”, and if larger than the depression/dimple maximum is 50µm/0.001969.”
For protrusions/bumps the number remains the same for any microvia diameter that is plated shut with a maximum protrusions/bumps of 25µm/0.000984.”
It is important to note that the Table 3-14 only applies to microvias in lands intended to be soldered at assembly. In all other microvia location that are not intended to be soldered at assembly the protrusion and dimples are not rejectable when all other conditions have been met.
If more stringent finished conditions are required, please document your AABUS (As Agreed Between User and Supplier) on your procurement documentation. For best practice please add your requirement on the fabrication drawing.
Please stay tuned for other changes in IPC-6012 rev F from Summit Interconnect.
Here is a picture of a microvia with a dimple.
And one with a protrusion.
For any further questions about changes in IPC-6012 Revision F or for technical questions, Summit Interconnect is here to assist. Email our field applications engineering team at email@example.com.