Cost Effective Means of Improving Signal Integrity
Backdrilling is a cost-effective method to improve signal integrity without adding costly additional sub-lamination structures. This process removes the unneeded portion of a via barrel that can cause signal reflections at high speed data rates, or on high frequency RF designs.
- Reduces deterministic jitter by orders of magnitude, resulting in lower Bit Error Rate.
- Reduces signal attenuation due to improved impedance matching.
- Reduces EMI/EMC radiation from the stub end and increasing channel bandwidth.
- Reduces excitation of resonance modes and via-to-via crosstalk.
- Reduces additional lamination structures.
- Minimizes design and layout impact with lower fabrication costs than sequential lamination.
- Improves microwave RF performance.
- Define which side to start the backdrill.
- Define “Must Not Cut” (MNC) layer. The MNC layer is the layer that must remain connected that is closest to the backdrill depth.
- Keep back distance from MNC layer minimum is .005” with a tolerance of +/-.002”, standard depth is .010”. Please review the signal performance to determine which depth is required.
- Backdrill diameter is typically .008” over the original drill bit used to create the plated via.
- Increase the copper clearance for the backdrilled layers an additional .004”.
- The MNC layer must be at least .010” away from the outer layer from the backdrill side of the PCB. This provides the minimum keep back distance to the MNC layer and provides minimum insulation distance to the outer layer.
Controlled Impedance Simulation
For Increasing Impedance Modeling Requirements
With the increasing speeds of modern circuitry, the demand for high-quality, controlled impedance printed circuit boards continues to grow. High-speed PCBs require accurate controlled impedance traces to operate reliably.
Summit Interconnect can help you verify your impedance design before it is released to manufacturing.
Our Impedance Simulator handles the common types of characteristic impedance requirements including:
- Differential impedance PCB structure
- Single-ended impedance modeling
- Microstrip and stripline constructions
- Coplannar Waveguides & Coplannar Waveguides with Ground
- 3D Field solvers (Boundary Element Method or BEM)
- Soldermask thickness between and adjacent to traces
Used in conjunction with our PCB Stack-Up modeling software, after defining an impedance tolerance, the system automatically generates the associated line widths and stack-up.
Create Uniform Distribution
A printed circuit board should be designed with balanced copper in mind. Copper balancing is necessary to achieve consistent flatness of the finished Printed Board. It also improves manufacturing yields by providing balanced copper plating distribution across each layer of the PCB. Balanced plating improves the consistency of through hole copper plating thickness and helps support the creation of uniform conductor and land thickness on plated layers. On inner layers, copper balancing helps to maintain dielectric thickness. Uniformity of the inner layers creates consistent overall thickness across the PCB. It reduces low pressure areas of the PCB that if not corrected can result in processing issues and require a redesign.
Copper Thickness and Resistance
Reduce Copper Thickness for Improved Yields
Outer layer copper thickness requirements should be reviewed as trace width and spacing decrease below .005”. Outer layer starting copper will determine the allowable space on a design. The thinner the base copper the finer space that is possible. The designer must consider the starting copper and hole copper plating requirement to determine the total outer layer copper on a finished PCB. IPC rules for minimum total copper of a plated outer layer is the starting copper minimum plus the minimum copper in the plated hole wall. For example if the outer layer starts with ½ ounce (minimum thickness after processing is .000512”) and the requirement in the hole is .001”, the minimum total outer layer copper must be .001512” or greater. (This information can be found in IPC-6012) The designer should try to utilize a copper callout to meet the electrical requirements as well as consider manufacturability of the PCB.
If you want to control the starting copper, simplly state on the fabrication the starting copper thickness. If the copper is stated as finished copper thickness Summit will select the most applicable starting copper to achieve the best yields for your design.
Copper weight is specified in ounces per square foot (taken from IPC 1401)
|Q||9 µm||0.34 mil|
|T||12 µm||0.5 mil|
|H||1/2 oz||0.70 mil|
|M||3/4 oz||1.0 mil|
|1||1 oz||1.4 mil|
|2||2 oz||2.8 mil|
|3||3 oz||4.2 mil|
The specification of 1/4, 3/8 and 1/2 ounce copper should be taken into consideration for improved manufacturability. The outer layer finished copper trace will be thicker than the starting copper because it includes the electroplated copper which is deposited in the holes and on the surface. During the etching process, only the starting copper thickness is etched away, not the plated surface copper. Total copper for plated layers is determined by the starting copper, and required copper plating in the plated holes. The total copper can be determined by reviewing IPC-6012 table 3-14.
Calculating copper resistance by thickness and length:
Resistance = (0.679×10-6 ohm/inch)
(width x thickness inches x length)
In fine line technology, using 0.5oz. copper, with a 5 mil trace and 5 inches long the resistivity will be:
((.679x 10-6)/(5x 0.7 x10-6)) x 5 = 0.97 Ω
Using Blind, Buried, and Stacked Vias on Complex Designs
Incorporating High Density Interconnect (HDI) structures is commonly utilized on advanced designs as a way to overcome space issues resulting from high I/O, fine pitch components. To achieve the density required in HDI designs, line width, spacing, hole diameters and pad sizes must all shrink. Reducing copper foil thickness on inner layers, reducing dielectric spacing to maintain low drill aspect ratios, incorporating via-in-pad and specifying the correct copper wrap are all critical factors in a successful design. However, for the most reliable structures, maintaining the following design guidelines will have the best results.
- Limit stacking of micro vias to 2-stack, if more than 2 stacked layers are required, stagger via layers
- Never stack microvias on top of buried vias
- Maintain a 6 mil micro via diameter, with a 12 mil capture pad
- Maintain an aspect ratio of .75:1 or less for microvias
- Specify .0002” copper wrap in the starting foil
- Copper fill microvias
- Design a D coupon that represents all via structures that can be tested for reliability using OM testing
Summit’s preferred method of testing HDI reliability is with OM testing.
This is a critical factor to determining the cost of a printed circuit board. The objective it to maximize the greatest amount of parts on a production panel using industry standard panel sizes of 12”x18”, 16”x18”, 18”x24” and 21”x24”. PCBs will be placed on the panel individually or in a sub-panel, referred to as an array. An array is commonly used if volume pick and place assembly is required. Careful thought must go into the design of the array to ensure that the panel area is maximized. A poorly conceived array can impact the final cost of the PCB significantly.
The size of the panel must also include all necessary validation “coupons”. The coupons will be created according to customer and industry specifications and will be placed in the border area of the panel. Depending on the number and type of coupons required, borders can range from 0.5” to 2.0” or more to accommodate the coupons. The more coupons required, the less space on the panel for PCBs. If requested, Summit will provide a production panel layout for your review prior to manufacturing. A list of industry standard coupons is below.
|A/B||Plated hole/via evaluation, size, spacing, registration, thermal stress″|
|Conformance||Rework simulation, bond strength, peel strength, dielectric withstanding
voltage, moisture/insulation resistance
|D||Reliability testing with OM test methods test methods IPC-TM-650 2.6.27|
|IST||Reliability testing with IST test methods IPC-TM-650 2.6.26|
|G||Validates solder mask adhesion|
Checking and Double Checking All of the Boxes
Once your order is placed at Summit, our pre-production team will verify the electrical integrity of your design by comparing your supplied CAD netlist to the design data. This process takes only minutes but will validate the design data and will confirm if all networks are connected and there are no broken nets or unintended shorts. Here are typical failures that we see:
- Isolated thermals
- Un-routed connections
- Split planes errors
- Unintentional shorts
Limiting EMI/RFI Interference
If your application requires limits in electromagnetic interference (EMI) or radiofrequency interference (RFI) or low voltage circuitry, the PCB needs to be designed with shielding. Shields are metal areas around a conductor or group of conductors that limit interference.
- Solid copper shielding
- Crosshatched copper shielding
- Solid conductive silver shielding
- Crosshatched conductive silver shielding
Conductive silver crosshatch shielding is not recommended for flex applications due to its brittle characteristic.
Shielding Design Considerations
- Shielding can be applied on both sides of a circuit or over selective conductors
- Solid copper shields increase circuit rigidity and must be included in the thickness-to-bend radius ratio for flex PCBs
- Copper crosshatch shielding is typically the best choice for flexible applications
Stack Up & Impedance Modeling
A preliminary stackup may have been created for you during the quote stage, but it must be validated against the final production data. Our engineers will use our automated Stack Up Builder quickly create graphical stack up that clearly shows material types, dielectric thicknesses, overall thickness, copper weights impedance. The Stackup Builder will access our extensive library of rigid, flex and prepreg materials to create a stackup that will meet your specifications. Alternative stackups can be quickly generated if you are looking to compare cost, performance, or juggle material lead times. To help, we have programmed cost based constraints to help you determine the most economical options that meet your print requirements. Summit is committed to utilizing the latest technology in engineering systems to speed you through the tooling process with precise results.
When designing your PCB, keep in mind the following best practices for the best stackup and ultimately most reliable PCB:
- Design multilayer PCBs with an even number of layers for balance
- Power and Ground layers should be balanced with respect to the center of the board
- Avoid uneven copper distribution on inner layers as it will impact the flatness of the board
- Create consistent dielectric thickness openings from the centerline of the PCB
- Copper layers should balance from centerline of board
Registration: All Summit facilities utilize Xact® Registration analysis tools to provide best in class registration for today’s demanding registration requirements.
Create Space for Pads and Improve Reliability
Via in pad with non-conductive epoxy improves signal performance for high speed digital and RF microwave applications. Summit also has experience with conductive epoxy filled vias and plated solid with copper. Summit can assist you with a cost effective method to meet your high speed, thermal management needs. Utilizing the latest via fill equipment, Summit can achieve epoxy fill for 8 mil vias with 15:1 aspect ratios. To fill microvias, plated shut copper vias is our preferred approach. Here are some things to keep in mind when incorporating filled vias in your design:
- Specify epoxy instead of metal based fill
- Specify copper fill on external layer microvias
- Design with low starting foil to reduce copper buildup throughout the sequential plating processes
Benefits of Via Fill
- Improved reliability by reducing the risk of trapped air or liquids
- Tighter BGA pitches and higher density interconnects by allowing for via-in-pad instead of dog bone designs. Summit Interconnect can support .25mm BGA requirements.
- Reliable filled and stacked via constructions.
- Planar copper surfaces above filled via for more reliable surface mounts and increased assembly yields.
- Enhanced thermal dissipation.