Technology Insights

Backdrilling

Cost Effective Means of Improving Signal Integrity 

Backdrilling is a cost-effective method to improve signal integrity without adding costly additional sub-lamination structures. This process removes the unneeded portion of a via barrel that can cause signal reflections at high speed data rates, or on high frequency RF designs.

Controlled Impedance Simulation

For Increasing Impedance Modeling Requirements

With the increasing speeds of modern circuitry, the demand for high-quality, controlled impedance printed circuit boards continues to grow. High-speed PCBs require accurate controlled impedance traces to operate reliably.

Summit Interconnect can help you verify your impedance design before it is released to manufacturing.

Our Impedance Simulator handles the common types of characteristic impedance requirements including:

• Differential impedance PCB structure
• Single-ended impedance modeling
• Microstrip and stripline constructions
• Coplannar Waveguides & Coplannar Waveguides with Ground
• 3D Field solvers (Boundary Element Method or BEM)
• Soldermask thickness between and adjacent to traces

Used in conjunction with our PCB Stack-Up modeling software, after defining an impedance tolerance, the system automatically generates the associated line widths and stack-up.

Copper Balancing

Create Uniform Distribution

A printed circuit board should be designed with balanced copper in mind. Copper balancing is necessary to achieve consistent flatness of the finished Printed Board. It also improves manufacturing yields by providing balanced copper plating distribution across each layer of the PCB. Balanced plating improves the consistency of through hole copper plating thickness and helps support the creation of uniform conductor and land thickness on plated layers. On inner layers, copper balancing helps to maintain dielectric thickness. Uniformity of the inner layers creates consistent overall thickness across the PCB. It reduces low pressure areas of the PCB that if not corrected can result in processing issues and require a redesign.

Copper Thickness and Resistance

Reduce Copper Thickness for Improved Yields 

Outer layer copper thickness requirements should be reviewed as trace width and spacing decrease below .005”. Outer layer starting copper will determine the allowable space on a design. The thinner the base copper the finer space that is possible. The designer must consider the starting copper and hole copper plating requirement to determine the total outer layer copper on a finished PCB. IPC rules for minimum total copper of a plated outer layer is the starting copper minimum plus the minimum copper in the plated hole wall. For example if the outer layer starts with ½ ounce (minimum thickness after processing is .000512”) and the requirement in the hole is .001”, the minimum total outer layer copper must be .001512” or greater. (This information can be found in IPC-6012) The designer should try to utilize a copper callout to meet the electrical requirements as well as consider manufacturability of the PCB.

If you want to control the starting copper, simplly state on the fabrication the starting copper thickness. If the copper is stated as finished copper thickness Summit will select the most applicable starting copper to achieve the best yields for your design.

HDI Structures

Using Blind, Buried, and Stacked Vias on Complex Designs

Incorporating High Density Interconnect (HDI) structures is commonly utilized on advanced designs as a way to overcome space issues resulting from high I/O, fine pitch components. To achieve the density required in HDI designs, line width, spacing, hole diameters and pad sizes must all shrink. Reducing copper foil thickness on inner layers, reducing dielectric spacing to maintain low drill aspect ratios, incorporating via-in-pad and specifying the correct copper wrap are all critical factors in a successful design. However, for the most reliable structures, maintaining the following design guidelines will have the best results.

• Limit stacking of micro vias to 2-stack, if more than 2 stacked layers are required, stagger via layers
• Never stack microvias on top of buried vias
• Maintain a 6 mil micro via diameter, with a 12 mil capture pad
• Maintain an aspect ratio of .75:1 or less for microvias
• Specify .0002” copper wrap in the starting foil
• Copper fill microvias
• Design a D coupon that represents all via structures that can be tested for reliability using OM testing

Summit’s preferred method of testing HDI reliability is with OM testing.

Panelization

Panelization

This is a critical factor to determining the cost of a printed circuit board. The objective it to maximize the greatest amount of parts on a production panel using industry standard panel sizes of 12”x18”, 16”x18”, 18”x24” and 21”x24”. PCBs will be placed on the panel individually or in a sub-panel, referred to as an array. An array is commonly used if volume pick and place assembly is required. Careful thought must go into the design of the array to ensure that the panel area is maximized. A poorly conceived array can impact the final cost of the PCB significantly.

The size of the panel must also include all necessary validation “coupons”. The coupons will be created according to customer and industry specifications and will be placed in the border area of the panel. Depending on the number and type of coupons required, borders can range from 0.5” to 2.0” or more to accommodate the coupons. The more coupons required, the less space on the panel for PCBs. If requested, Summit will provide a production panel layout for your review prior to manufacturing. A list of industry standard coupons is below.

Production Tooling

Checking and Double Checking All of the Boxes

Once your order is placed at Summit, our pre-production team will verify the electrical integrity of your design by comparing your supplied CAD netlist to the design data. This process takes only minutes but will validate the design data and will confirm if all networks are connected and there are no broken nets or unintended shorts. Here are typical failures that we see:

• Isolated thermals
• Un-routed connections
• Split planes errors
• Unintentional shorts

Shielding

Limiting EMI/RFI Interference

If your application requires limits in electromagnetic interference (EMI) or radiofrequency interference (RFI) or low voltage circuitry, the PCB needs to be designed with shielding. Shields are metal areas around a conductor or group of conductors that limit interference.

Stack Up & Impedance Modeling

A preliminary stackup may have been created for you during the quote stage, but it must be validated against the final production data. Our engineers will use our automated Stack Up Builder quickly create graphical stack up that clearly shows material types, dielectric thicknesses, overall thickness, copper weights impedance. The Stackup Builder will access our extensive library of rigid, flex and prepreg materials to create a stackup that will meet your specifications. Alternative stackups can be quickly generated if you are looking to compare cost, performance, or juggle material lead times. To help, we have programmed cost based constraints to help you determine the most economical options that meet your print requirements. Summit is committed to utilizing the latest technology in engineering systems to speed you through the tooling process with precise results.

When designing your PCB, keep in mind the following best practices for the best stackup and ultimately most reliable PCB:

• Design multilayer PCBs with an even number of layers for balance
• Power and Ground layers should be balanced with respect to the center of the board
• Avoid uneven copper distribution on inner layers as it will impact the flatness of the board
• Create consistent dielectric thickness openings from the centerline of the PCB
• Copper layers should balance from centerline of board

Registration: All Summit facilities utilize Xact® Registration analysis tools to provide best in class registration for today’s demanding registration requirements.

Via Fill

Create Space for Pads and Improve Reliability